`timescale 1ns / 1ps module sprite(CLK_50M, VGA_R, VGA_G, VGA_B, VGA_HSYNC, VGA_VSYNC, LED, SW, BTN_NORTH, BTN_SOUTH, BTN_WEST, BTN_EAST, ROT_CENTER); input CLK_50M; output [3:0] VGA_R; output [3:0] VGA_G; output [3:0] VGA_B; output VGA_HSYNC; output VGA_VSYNC; output [7:0] LED; input [3:0] SW; input BTN_NORTH; input BTN_SOUTH; input BTN_WEST; input BTN_EAST; input ROT_CENTER; wire reset; assign reset = ROT_CENTER; reg [1:0] clock_count; wire clk; assign clk = clock_count[0]; reg [9:0] hcount; reg [9:0] vcount; wire [9:0] x; wire [9:0] y; assign x = hcount; assign y = vcount; // reg [3:0] vga_r_out; // reg [3:0] vga_g_out; // reg [3:0] vga_b_out; reg vga_r_out; reg vga_g_out; reg vga_b_out; reg vga_hsync_out; reg vga_vsync_out; // assign VGA_R = vga_r_out; // assign VGA_G = vga_g_out; // assign VGA_B = vga_b_out; assign VGA_R[3:0] = { vga_r_out, vga_r_out, vga_r_out, vga_r_out }; assign VGA_G[3:0] = { vga_g_out, vga_g_out, vga_g_out, vga_g_out }; assign VGA_B[3:0] = { vga_b_out, vga_b_out, vga_b_out, vga_b_out }; assign VGA_HSYNC = vga_hsync_out; assign VGA_VSYNC = vga_vsync_out; parameter H_ACTIVE_PIXEL_LIMIT = 640; parameter H_FPORCH_PIXEL_LIMIT = 656; // 640+16 parameter H_SYNC_PIXEL_LIMIT = 752; // 640+16+96 parameter H_BPORCH_PIXEL_LIMIT = 800; // 640+16+96+48 parameter V_ACTIVE_LINE_LIMIT = 480; parameter V_FPORCH_LINE_LIMIT = 490; // 480+10 parameter V_SYNC_LINE_LIMIT = 492; // 480+10+2 parameter V_BPORCH_LINE_LIMIT = 521; // 480+10+2+29 reg [1023:0] spbitmap; // 16x16x4 reg [9:0] spreg_dx; reg [9:0] spreg_dy; wire [1:0] spreg_mx; wire [1:0] spreg_my; assign spreg_mx = SW[1:0]; assign spreg_my = SW[3:2]; assign LED[7:0] = 8'b00000000; always @* begin if (reset) begin spbitmap[ 63: 0] <= 64'h0000000000000000; spbitmap[ 127: 64] <= 64'h0000007777000000; spbitmap[ 191:128] <= 64'h0000777777770000; spbitmap[ 255:192] <= 64'h0000777777770000; spbitmap[ 319:256] <= 64'h0000007777000000; spbitmap[ 383:320] <= 64'h0770000770000770; spbitmap[ 447:384] <= 64'h0770000770000770; spbitmap[ 511:448] <= 64'h0777777777777770; spbitmap[ 575:512] <= 64'h0777777777777770; spbitmap[ 639:576] <= 64'h0000001111000000; spbitmap[ 703:640] <= 64'h0000001111000000; spbitmap[ 767:704] <= 64'h0000002222000000; spbitmap[ 831:768] <= 64'h0000022222200000; spbitmap[ 895:832] <= 64'h0000222002220000; spbitmap[ 959:896] <= 64'h0002220000222000; spbitmap[1023:960] <= 64'h2222220000222222; spreg_dx <= 0; spreg_dy <= 0; end else if (BTN_NORTH) begin spreg_dy <= spreg_dy - 1; end else if (BTN_SOUTH) begin spreg_dy <= spreg_dy + 1; end else if (BTN_WEST) begin spreg_dx <= spreg_dx - 1; end else if (BTN_EAST) begin spreg_dx <= spreg_dx + 1; end end always @(posedge CLK_50M) begin clock_count <= clock_count + 1; end always @(posedge clk) begin if (hcount < H_BPORCH_PIXEL_LIMIT) hcount <= hcount + 1; else begin hcount <= 0; if (vcount < V_BPORCH_LINE_LIMIT) vcount <= vcount + 1; else vcount <= 0; end if (hcount < H_ACTIVE_PIXEL_LIMIT && vcount < V_ACTIVE_LINE_LIMIT) // active video begin if ((((y - spreg_dy) >> spreg_my) < 16) && (((x - spreg_dx) >> spreg_mx) < 16)) begin if (spbitmap[(((y - spreg_dy) >> spreg_my) << 6) | (((x - spreg_dx) >> spreg_mx) << 2) | 2'b11] == 1'b0) begin vga_b_out <= spbitmap[(((y - spreg_dy) >> spreg_my) << 6) | (((x - spreg_dx) >> spreg_mx) << 2) | 2'b00]; vga_r_out <= spbitmap[(((y - spreg_dy) >> spreg_my) << 6) | (((x - spreg_dx) >> spreg_mx) << 2) | 2'b01]; vga_g_out <= spbitmap[(((y - spreg_dy) >> spreg_my) << 6) | (((x - spreg_dx) >> spreg_mx) << 2) | 2'b10]; end else begin vga_b_out <= 0; vga_r_out <= 0; vga_g_out <= 0; end end else begin vga_b_out <= 0; vga_r_out <= 0; vga_g_out <= 0; end end else case (hcount) H_ACTIVE_PIXEL_LIMIT : // front porch begin vga_r_out <= 4'd0; vga_g_out <= 4'd0; vga_b_out <= 4'd0; end H_FPORCH_PIXEL_LIMIT : // sync pulse vga_hsync_out <= 1'b0; H_SYNC_PIXEL_LIMIT : // back porch vga_hsync_out <= 1'b1; endcase case (vcount) V_ACTIVE_LINE_LIMIT : // front porch ; V_FPORCH_LINE_LIMIT : // sync pulse vga_vsync_out <= 1'b0; V_SYNC_LINE_LIMIT : // back porch vga_vsync_out <= 1'b1; endcase end endmodule